AND Gate

From ReliaWiki
Revision as of 00:35, 16 July 2011 by Pantelis (talk | contribs)
Jump to navigation Jump to search

This page describes the AND gate and it's applications in Fault Tree diagrams used in Reliability and Safety Engineering.

In an AND gate, the output event occurs if all input events occur (or event A AND event B AND event C). When used in reliability and safety engineering an event is usualy a failure, a failure mode, or other undesirable event.

If one is looking at system reliability with each event represnting a component of the system then this this implies that all components must fail (input) in order for the system to fail (output). When using RBDs, the equivalent is a simple parallel configuration.

Andgate.png


System Reliability Example

Consider a system with two components, A and B. The system fails if both [math]\displaystyle{ A }[/math] and [math]\displaystyle{ B }[/math] fail. Draw the fault tree and reliability block diagram for the system. The next two figures show both the FTD and RBD representations.

I10.2.gif
I10.3.gif



The reliability equation for either configuration is:


[math]\displaystyle{ {{R}_{System}}={{R}_{A}}+{{R}_{B}}-{{R}_{A}}\cdot {{R}_{B}} }[/math]