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| RCM++ allows you to add a design verification plan and report (DVP&R) analysis for any item in the system hierarchy. A DVP&R is a worksheet that is used to track the progress of design verification tests. The lessons learned from the Design FMEA can be a valuable input to the DVP&R (and vice-versa). | |
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| | [http://help.synthesis8.com/rcm8/index.htm#design_verification_plans_(dvp&rs).htm the help files...]
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| | [http://www.weibull.com/basics/rcm.htm the theory textbook...]
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| | [http://www.reliawiki.com/index.php/Temporary_needs_example_page use example(s)...]
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| [[Category:Needs example]]
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